SymbiFlow
Table Of Contents
SymbiFlow
Table Of Contents

Introduction

SymbiFlow is a Open Source Verilog-to-Bitstream FPGA synthesis flow, currently targeting Xilinx 7-Series, Lattice iCE40 and Lattice ECP5 FPGAs. Think of it as the GCC of FPGAs.

module ram0( // Write port input wrclk, input [15:0] di, input wren, input [9:0] wraddr, // Read port input rdclk, input rden, input [9:0] rdaddr, output reg [15:0] do); (* ram_style = "block" *) reg [15:0] ram[0:1023]; initial begin ram[0] = 16'b00000000_00000001; ram[1] = 16'b10101010_10101010; ram[2] = 16'b01010101_01010101; ram[3] = 16'b11111111_11111111; ram[4] = 16'b11110000_11110000; ram[5] = 16'b00001111_00001111; ram[6] = 16'b11001100_11001100; ram[7] = 16'b00110011_00110011; ram[8] = 16'b00000000_00000010; ram[9] = 16'b00000000_00000100; end always @ (posedge wrclk) begin if(wren == 1) begin ram[wraddr] <= di; end end always @ (posedge rdclk) begin if(rden == 1) begin do <= ram[rdaddr]; end end endmodule module top ( input clk, input [15:0] in, output [15:0] out ); wire rden; reg wren; wire [9:0] rdaddr; wire [9:0] wraddr; wire [15:0] di; wire [15:0] do; ram0 ram( .wrclk(clk), .di(di), .wren(wren), .wraddr(wraddr), .rdclk(clk), .rden(rden), .rdaddr(rdaddr), .do(do) ); reg [9:0] address_reg; reg [15:0] data_reg; reg [15:0] out_reg; assign rdaddr = address_reg; assign wraddr = address_reg; // display_mode == 00 -> ram[address_reg] // display_mode == 01 -> address_reg // display_mode == 10 -> data_reg wire [1:0] display_mode; // input_mode == 00 -> in[9:0] -> address_reg // input_mode == 01 -> in[7:0] -> data_reg[7:0] // input_mode == 10 -> in[7:0] -> data_reg[15:8] // input_mode == 11 -> data_reg -> ram[address_reg] wire [1:0] input_mode; // WE == 0 -> address_reg and data_reg unchanged. // WE == 1 -> address_reg or data_reg is updated because on input_mode. wire we; assign display_mode[0] = in[14]; assign display_mode[1] = in[15]; assign input_mode[0] = in[12]; assign input_mode[1] = in[13]; assign we = in[11]; assign out = out_reg; assign di = data_reg; assign rden = 1; initial begin address_reg = 10'b0; data_reg = 16'b0; out_reg = 16'b0; end always @ (posedge clk) begin if(display_mode == 0) begin out_reg <= do; end else if(display_mode == 1) begin out_reg <= address_reg; end else if(display_mode == 2) begin out_reg <= data_reg; end if(we == 1) begin if(input_mode == 0) begin address_reg <= in[9:0]; wren <= 0; end else if(input_mode == 1) begin data_reg[7:0] <= in[7:0]; wren <= 0; end else if(input_mode == 2) begin data_reg[15:8] <= in[7:0]; wren <= 0; end else if(input_mode == 3) begin wren <= 1; end end end endmodule

The project aim is to design tools that are highly extendable and multiplatform.

EDA Tooling Ecosystem

For both ASIC- and FPGA-oriented EDA tooling, there are three major areas that the workflow needs to cover: hardware description, frontend and backend.

Hardware description languages are generally open, with both established HDLs such as Verilog and VHDL and emerging software-inspired paradigms like Chisel, SpinalHDL or Migen. The major problem lies however in the front- and backend, where previously there was no established standard, vendor-neutral tooling that would cover all the necessary components for an end-to-end flow.

This pertains both to ASIC and FPGA workflows, although SymbiFlow focuses on the latter (some parts of SymbiFlow will also be useful in the former).

_images/EDA.svg

Project structure

To achieve SymbiFlow’s goal of a complete FOSS FPGA toolchain, a number of tools and projects are necessary to provide all the needed components of an end-to-end flow. Thus, SymbiFlow serves as an umbrella project for several activities, the central of which pertains to the creation of so-called FPGA “architecture definitions”, i.e. documentation of how specific FPGAs work internally. More information can be found in the Symbiflow Architecture Definitions project.

Those definitions and serve as input to backend tools like nextpnr and Verilog to Routing, and frontend tools like Yosys. They are created within separate collaborating projects targeting different FPGAs - Project X-Ray for Xilinx 7-Series, Project IceStorm for Lattice iCE40 and Project Trellis for Lattice ECP5 FPGAs.

_images/parts.svg

Current status of bitstream documentation

Projects

IceStorm

X-Ray

Trellis

Basic Tiles

Logic

Yes

Yes

Yes

Block RAM

Yes

Partial

N/A

Advanced Tiles

DSP

Yes

No

Yes

Hard Blocks

Yes

No

Yes

Clock Tiles

Yes

Partial

Yes

IO Tiles

Yes

Partial

Yes

Routing

Logic

Yes

Yes

Yes

Clock

Yes

Partial

Yes

Table Of Contents

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