SymbiFlow

Table Of Contents

Toolchain description

This section provides a description of the Symbiflow toolchain as well as the basic concepts of the FPGA design flow.

• Getting Started
  • Clone repository
  • Prepare environment
  • Build example
  • Load bitstream
    • Vivado
    • xc3sprog
• FPGA Design Flow
  • Synthesis
    • RTL Generation
    • Technology mapping
    • Optimization
    • Synthesis in SymbiFlow
  • Place & Route
    • Packing
    • Placing
    • Routing
    • Analysis
    • Place & Route in SymbiFlow
  • Bitstream translation
• Yosys
  • Short description
  • Usage in Toolchain
  • Output analysis
  • More information
• VPR
  • Basic flow
    • Packing
    • Placement
    • Routing
    • Analysis
  • Command-line Options
    • Basic Usage
    • Detailed Command-line Options
  • Graphics
    • Enabling Graphics
    • Navigation
    • Visualizing Netlist Connectivity
    • Visualizing Routing Architecture
    • Visualizing Routing Congestion
    • Visualizing the Critical Path
    • Button Description Table
  • Timing Constraints
    • Default Timing Constraints
  • SDC Commands
    • create_clock
    • set_clock_groups
    • set_false_path
    • set_max_delay/set_min_delay
    • set_multicycle_path
    • set_input_delay/set_output_delay
    • set_clock_uncertainty
    • set_clock_latency
    • set_disable_timing
    • Special Characters
    • SDC Examples
  • File Formats
    • FPGA Architecture (.xml)
    • BLIF Netlist (.blif)
    • Extended BLIF (.eblif)
    • Timing Constraints (.sdc)
    • Packed Netlist Format (.net)
    • Placement File Format (.place)
    • Routing File Format (.route)
    • Routing Resource Graph File Format (.xml)
  • Debugging Aids

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Getting Started